Semiconductor based integrated circuits dies are created from a silicon wafer through the employment of various etching, doping, and depositing steps that are well known in the art. Ultimately, the integrated circuit may be packaged by forming an encapsulant around the integrated circuit so as to form a "packaged integrated circuit" having a variety of pinouts or mounting and interconnection schemes. Plastic is often utilized as an encapsulant. Integrated circuit packages that utilize plastic as an encapsulant are generally less expensive than other packaging options.
A multichip module is a package having related integrated circuits bonded together in a single package. Typically, the integrated circuits are placed side to side and electrically coupled together using, for example, a substrate or leadframe. This arrangement, however, can, and usually does, result in the multichip module having a large footprint (module's surface area). The large footprint restricts the use of the multichip module to only those applications for which a large footprint is not a substantial problem. However, in such devices as handsets, cordless phone base stations, etc. it is critically important that the footprint of any packaged integrated circuit be reduced as much as possible.
Recent efforts to reduce the footprint of multichip package modules has resulted in a particular multichip module configuration referred to as a chip on chip package module. A chip on chip module is formed by stacking one chip, or chips, atop one another and electrically connecting them by way of corresponding interchip bond pads. One such arrangement is shown in FIG. 1 illustrating a chip on chip module 100 exemplary of a digital signal processing (DSP) module manufactured by the APack Corporation of Taichung City, Taiwan, R.O.C. A daughter chip 102 in the form of a static random access memory integrated circuit is stacked on top of a mother chip 104 in the form of a digital signal processor (DSP). The daughter chip 102 and the mother chip 104 are electrically coupled to each other by way of corresponding interchip bond pads 106 and 108, respectively.
Conventional bonding practices call for each of the bond pads 106 to have a solder ball deposited thereupon which then is used to electrically couple the bond pad 106 to the corresponding bond pad 108 during a subsequent solder reflow operation. A low viscosity insulative material, referred to as fillant 110 or underfill resin, by capillary action alone, fills the region referred to as a standoff 112, or standoff gap, that lies between the daughter chip 102 and the mother chip. Typically, in order for the fillant 110 to flow by capillary action, it's viscosity value ranges from 2,000 to 10,000 cP. Once electrically coupled to the daughter chip 102, bond wires 114 are used to electrically couple bond pads 116 on the mother chip 104 to corresponding leads 118.
Unfortunately, due to the fact that the viscosity of the fillant 110 is an order of magnitude less than that of standard encapsulant, the chip on chip module 100 must be packaged in a ceramic type package 120 which reduces the reliability of the chip on chip module 100 and increases the cost. In addition, the requirement to use a low viscosity fillant 110 requires a multistep encapsulating process where precious manufacturing time and expense is used to manually fill the standoff.
In view of the foregoing, it would be desirable to provide more efficient arrangements for encapsulating chip on chip modules.